? arch/arm/feroceon
? arch/evbarm/kuroboxarm
? arch/evbarm/conf/KUROBOXARM
? arch/evbarm/conf/files.kuroboxarm
? arch/evbarm/conf/mk.kuroboxarm
? arch/evbarm/conf/std.kuroboxarm
Index: dev/mii/makphy.c
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/makphy.c,v
retrieving revision 1.24
diff -u -r1.24 makphy.c
--- dev/mii/makphy.c	9 Dec 2007 20:28:03 -0000	1.24
+++ dev/mii/makphy.c	31 Dec 2007 14:12:37 -0000
@@ -104,6 +104,45 @@
 };
 
 static const struct mii_phydesc makphys[] = {
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1000,
+	  MII_STR_MARVELL_E1000 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1011,
+	  MII_STR_MARVELL_E1011 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1000_3,
+	  MII_STR_MARVELL_E1000_3 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1000S,
+	  MII_STR_MARVELL_E1000S },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1000_5,
+	  MII_STR_MARVELL_E1000_5 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1000_6,
+	  MII_STR_MARVELL_E1000_6 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E3082,
+	  MII_STR_MARVELL_E3082 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1112,
+	  MII_STR_MARVELL_E1112 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1149,
+	  MII_STR_MARVELL_E1149 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1111,
+	  MII_STR_MARVELL_E1111 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1116,
+	  MII_STR_MARVELL_E1116 },
+
+	{ MII_OUI_MARVELL,		MII_MODEL_MARVELL_E1118,
+	  MII_STR_MARVELL_E1118 },
+
+	{ MII_OUI_xxMARVELL,		MII_MODEL_xxMARVELL_E1011,
+	  MII_STR_xxMARVELL_E1011 },
+
 	{ MII_OUI_xxMARVELL,		MII_MODEL_xxMARVELL_E1000_3,
 	  MII_STR_xxMARVELL_E1000_3 },
 
@@ -116,6 +155,9 @@
 	{ MII_OUI_xxMARVELL,		MII_MODEL_xxMARVELL_E1111,
 	  MII_STR_xxMARVELL_E1111 },
 
+	{ MII_OUI_xxMARVELL,		MII_MODEL_xxMARVELL_E1118,
+	  MII_STR_xxMARVELL_E1118 },
+
 	{ 0,				0,
 	  NULL },
 };
@@ -139,6 +181,7 @@
 	struct mii_attach_args *ma = aux;
 	struct mii_data *mii = ma->mii_data;
 	const struct mii_phydesc *mpd;
+	int reg, page;
 
 	mpd = mii_phy_match(ma, makphys);
 	aprint_naive(": Media interface\n");
@@ -151,19 +194,105 @@
 	sc->mii_flags = ma->mii_flags;
 	sc->mii_anegticks = MII_ANEGTICKS;
 
-	PHY_RESET(sc);
+	if (MII_MODEL(ma->mii_id2) == MII_MODEL_MARVELL_E1111 &&
+	    !(sc->mii_flags & MIIF_HAVEFIBER)) {
+		/*
+		 * The onboard 88E1111 PHYs on the Sun X4100 M2 come
+		 * up with fiber/copper auto-selection enabled, even
+		 * though the machine only has copper ports.  This
+		 * makes the chip autoselect to 1000baseX, and makes
+		 * it impossible to select any other media.  So
+		 * disable fiber/copper autoselection.
+		 */
+		reg = PHY_READ(sc, MII_MAKPHY_ESSR);
+		if ((reg & ESSR_HWCFG_MODE) == ESSR_RGMII_COPPER) {
+			reg |= ESSR_DIS_FC;
+			PHY_WRITE(sc, MII_MAKPHY_ESSR, reg);
+
+			PHY_RESET(sc);
+		}
+	}
 
-	sc->mii_capabilities =
-	    PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
+	/* Switch to fiber-only mode if necessary. */
+	if (MII_MODEL(ma->mii_id2) == MII_MODEL_MARVELL_E1112 &&
+	    sc->mii_flags & MIIF_HAVEFIBER) {
+		page = PHY_READ(sc, MII_MAKPHY_EADR);
+		PHY_WRITE(sc, MII_MAKPHY_EADR, 2);
+		reg = PHY_READ(sc, MII_MAKPHY_PSCR);
+		reg &= ~PSCR_MODE_MASK;
+		reg |= PSCR_MODE_1000BX;
+		PHY_WRITE(sc, MII_MAKPHY_PSCR, reg);
+		PHY_WRITE(sc, MII_MAKPHY_EADR, page);
+
+		PHY_RESET(sc);
+	}
+
+	sc->mii_capabilities = PHY_READ(sc, MII_BMSR) & ma->mii_capmask;
 	if (sc->mii_capabilities & BMSR_EXTSTAT)
 		sc->mii_extcapabilities = PHY_READ(sc, MII_EXTSR);
 
 	aprint_normal("%s: ", sc->mii_dev.dv_xname);
 	if ((sc->mii_capabilities & BMSR_MEDIAMASK) == 0 &&
-	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0)
-		aprint_error("no media present");
-	else
+	    (sc->mii_extcapabilities & EXTSR_MEDIAMASK) == 0) {
+		aprint_error("no media present\n");
+		return;
+	} else
 		mii_phy_add_media(sc);
+
+	/*
+	 * Initialize PHY Specific Control Register.
+	 */
+
+	reg = PHY_READ(sc, MII_MAKPHY_PSCR);
+
+	/* Assert CRS on transmit. */
+	reg |= PSCR_CRS_ON_TX;
+
+	/* Enable auto crossover. */
+	switch (MII_MODEL(ma->mii_id2)) {
+	case MII_MODEL_MARVELL_E3082:
+		/* Bits are in a different position. */
+		reg |= (PSCR_MDI_XOVER_MODE(XOVER_MODE_MDIX |
+		    XOVER_MODE_AUTO) >> 1);
+		break;
+
+	default:
+		/* Automatic crossover causes problems for 1000baseX. */
+		if (sc->mii_flags & MIIF_IS_1000X)
+			reg &= ~PSCR_MDI_XOVER_MODE(XOVER_MODE_MDIX |
+			    XOVER_MODE_AUTO);
+		else
+			reg |= PSCR_MDI_XOVER_MODE(XOVER_MODE_MDIX |
+			    XOVER_MODE_AUTO);
+	}
+
+	/* Disable energy detect; only available on some models. */
+	switch(MII_MODEL(ma->mii_id2)) {
+	case MII_MODEL_MARVELL_E1011:
+	case MII_MODEL_MARVELL_E1111:
+	case MII_MODEL_MARVELL_E1112:
+		/* Disable energy detect. */
+		reg &= ~PSCR_EN_DETECT_MASK;
+		break;
+	}
+
+	PHY_WRITE(sc, MII_MAKPHY_PSCR, reg);
+
+	/* 25 MHz TX_CLK should always work. */
+	reg = PHY_READ(sc, MII_MAKPHY_EPSC);
+	reg |= EPSC_TX_CLK(7);	/* 25MHz */
+	PHY_WRITE(sc, MII_MAKPHY_EPSC, reg);
+
+	/*
+	 * Do a software reset for these settings to take effect.
+	 * Disable autonegotiation, such that all capabilities get
+	 * advertised when it is switched back on.
+	 */
+	reg = PHY_READ(sc, MII_BMCR);
+	reg &= ~BMCR_AUTOEN;
+	PHY_WRITE(sc, MII_BMCR, reg | BMCR_RESET);
+	PHY_WRITE(sc, MII_BMCR, reg);
+
 	aprint_normal("\n");
 
 	if (!pmf_device_register(self, NULL, mii_phy_resume))
Index: dev/mii/makphyreg.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/makphyreg.h,v
retrieving revision 1.2
diff -u -r1.2 makphyreg.h
--- dev/mii/makphyreg.h	25 Dec 2006 18:41:45 -0000	1.2
+++ dev/mii/makphyreg.h	31 Dec 2007 14:12:37 -0000
@@ -60,6 +60,14 @@
 #define	XOVER_MODE_MDIX		1
 #define	XOVER_MODE_AUTO		2
 
+#define PSCR_EN_DETECT_MASK	0x0300
+
+/* page 2 */
+#define PSCR_MODE_MASK		0x0380
+#define PSCR_MODE_AUTO		0x0180
+#define PSCR_MODE_COPPER	0x0280
+#define PSCR_MODE_1000BX	0x0380
+
 #define	MII_MAKPHY_PSSR		0x11	/* PHY specific status register */
 #define	PSSR_JABBER		(1U << 0)   /* jabber indication */
 #define	PSSR_POLARITY		(1U << 1)   /* polarity indiciation */
@@ -101,6 +109,8 @@
 
 #define	MII_MAKPHY_REC		0x15	/* receive error counter */
 
+#define MII_MAKPHY_EADR		0x16	/* extended address reg */
+
 #define	MII_MAKPHY_LEDCTRL	0x18	/* LED control */
 #define	LEDCTRL_LED_TX		(1U << 0)   /* 1 = activ/link, 0 = xmit */
 #define	LEDCTRL_LED_RX		(1U << 1)   /* 1 = activ/link, 1 = recv */
@@ -110,4 +120,14 @@
 #define	LEDCTRL_PULSE_STRCH(x)	((x) << 12)
 #define	LEDCTRL_DISABLE		(1U << 15)  /* disable LED */
 
+#define MII_MAKPHY_ESSR		0x1b	/* Extended PHY specific sts */
+#define ESSR_HWCFG_MODE		0x000f
+#define ESSR_GMII_COPPER	0x000f
+#define ESSR_GMII_FIBER		0x0007
+#define ESSR_TBI_COPPER		0x000d
+#define ESSR_TBI_FIBER		0x0005
+#define ESSR_RGMII_COPPER	0x000b
+#define ESSR_FIBER_LINK		(1U << 13)
+#define ESSR_DIS_FC		(1U << 15)
+
 #endif /* _DEV_MII_MAKPHYREG_H_ */
Index: dev/mii/miidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs,v
retrieving revision 1.73
diff -u -r1.73 miidevs
--- dev/mii/miidevs	12 Oct 2007 10:13:07 -0000	1.73
+++ dev/mii/miidevs	31 Dec 2007 14:12:37 -0000
@@ -188,11 +188,24 @@
 model LEVEL1 LXT1000		0x000c LXT1000 1000BASE-T media interface
 
 /* Marvell Semiconductor PHYs */
+model MARVELL E1000		0x0000 Marvell 88E1000 Gigabit PHY
+model MARVELL E1011		0x0002 Marvell 88E1011 Gigabit PHY
+model MARVELL E1000_3		0x0003 Marvell 88E1000 Gigabit PHY
+model MARVELL E1000S		0x0004 Marvell 88E1000S Gigabit PHY
+model MARVELL E1000_5		0x0005 Marvell 88E1000 Gigabit PHY
+model MARVELL E1000_6		0x0006 Marvell 88E1000 Gigabit PHY
+model MARVELL E3082		0x0008 Marvell 88E3082 Gigabit PHY
+model MARVELL E1112		0x0009 Marvell 88E1112 Gigabit PHY
+model MARVELL E1149		0x000b Marvell 88E1149 Gigabit PHY
+model MARVELL E1111		0x000c Marvell 88E1111 Gigabit PHY
+model MARVELL E1116		0x0021 Marvell 88E1116 Gigabit PHY
+model MARVELL E1118		0x0022 Marvell 88E1118 Gigabit PHY
 model xxMARVELL E1011		0x0002 Marvell 88E1011 Gigabit PHY
 model xxMARVELL E1000_3		0x0003 Marvell 88E1000 Gigabit PHY
 model xxMARVELL E1000_5		0x0005 Marvell 88E1000 Gigabit PHY
 model xxMARVELL E6060		0x0008 Marvell 88E6060 10/100 5-port PHY switch
 model xxMARVELL E1111		0x000c Marvell 88E1111 Gigabit PHY
+model xxMARVELL E1118		0x0021 Marvell 88E1116 Gigabit PHY
 
 /* Myson Technology PHYs */
 model xxMYSON MTD972		0x0000 MTD972 10/100 media interface
Index: dev/mii/miidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs.h,v
retrieving revision 1.76
diff -u -r1.76 miidevs.h
--- dev/mii/miidevs.h	12 Oct 2007 10:14:03 -0000	1.76
+++ dev/mii/miidevs.h	31 Dec 2007 14:12:37 -0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: miidevs.h,v 1.76 2007/10/12 10:14:03 tsutsui Exp $	*/
+/*	$NetBSD$	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
@@ -253,6 +253,30 @@
 #define	MII_STR_LEVEL1_LXT1000	"LXT1000 1000BASE-T media interface"
 
 /* Marvell Semiconductor PHYs */
+#define	MII_MODEL_MARVELL_E1000	0x0000
+#define	MII_STR_MARVELL_E1000	"Marvell 88E1000 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1011	0x0002
+#define	MII_STR_MARVELL_E1011	"Marvell 88E1011 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_3	0x0003
+#define	MII_STR_MARVELL_E1000_3	"Marvell 88E1000 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000S	0x0004
+#define	MII_STR_MARVELL_E1000S	"Marvell 88E1000S Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_5	0x0005
+#define	MII_STR_MARVELL_E1000_5	"Marvell 88E1000 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1000_6	0x0006
+#define	MII_STR_MARVELL_E1000_6	"Marvell 88E1000 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E3082	0x0008
+#define	MII_STR_MARVELL_E3082	"Marvell 88E3082 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1112	0x0009
+#define	MII_STR_MARVELL_E1112	"Marvell 88E1112 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1149	0x000b
+#define	MII_STR_MARVELL_E1149	"Marvell 88E1149 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1111	0x000c
+#define	MII_STR_MARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1116	0x0021
+#define	MII_STR_MARVELL_E1116	"Marvell 88E1116 Gigabit PHY"
+#define	MII_MODEL_MARVELL_E1118	0x0022
+#define	MII_STR_MARVELL_E1118	"Marvell 88E1118 Gigabit PHY"
 #define	MII_MODEL_xxMARVELL_E1011	0x0002
 #define	MII_STR_xxMARVELL_E1011	"Marvell 88E1011 Gigabit PHY"
 #define	MII_MODEL_xxMARVELL_E1000_3	0x0003
@@ -263,6 +287,8 @@
 #define	MII_STR_xxMARVELL_E6060	"Marvell 88E6060 10/100 5-port PHY switch"
 #define	MII_MODEL_xxMARVELL_E1111	0x000c
 #define	MII_STR_xxMARVELL_E1111	"Marvell 88E1111 Gigabit PHY"
+#define	MII_MODEL_xxMARVELL_E1118	0x0021
+#define	MII_STR_xxMARVELL_E1118	"Marvell 88E1116 Gigabit PHY"
 
 /* Myson Technology PHYs */
 #define	MII_MODEL_xxMYSON_MTD972	0x0000
Index: dev/mii/miidevs_data.h
===================================================================
RCS file: /cvsroot/src/sys/dev/mii/miidevs_data.h,v
retrieving revision 1.66
diff -u -r1.66 miidevs_data.h
--- dev/mii/miidevs_data.h	12 Oct 2007 10:14:04 -0000	1.66
+++ dev/mii/miidevs_data.h	31 Dec 2007 14:12:37 -0000
@@ -1,4 +1,4 @@
-/*	$NetBSD: miidevs_data.h,v 1.66 2007/10/12 10:14:04 tsutsui Exp $	*/
+/*	$NetBSD$	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
@@ -102,11 +102,24 @@
  { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT975, MII_STR_LEVEL1_LXT975 },
  { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000_OLD, MII_STR_LEVEL1_LXT1000_OLD },
  { MII_OUI_LEVEL1, MII_MODEL_LEVEL1_LXT1000, MII_STR_LEVEL1_LXT1000 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000, MII_STR_MARVELL_E1000 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1011, MII_STR_MARVELL_E1011 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_3, MII_STR_MARVELL_E1000_3 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000S, MII_STR_MARVELL_E1000S },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_5, MII_STR_MARVELL_E1000_5 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1000_6, MII_STR_MARVELL_E1000_6 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E3082, MII_STR_MARVELL_E3082 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1112, MII_STR_MARVELL_E1112 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1149, MII_STR_MARVELL_E1149 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1111, MII_STR_MARVELL_E1111 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1116, MII_STR_MARVELL_E1116 },
+ { MII_OUI_MARVELL, MII_MODEL_MARVELL_E1118, MII_STR_MARVELL_E1118 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1011, MII_STR_xxMARVELL_E1011 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_3, MII_STR_xxMARVELL_E1000_3 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1000_5, MII_STR_xxMARVELL_E1000_5 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E6060, MII_STR_xxMARVELL_E6060 },
  { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1111, MII_STR_xxMARVELL_E1111 },
+ { MII_OUI_xxMARVELL, MII_MODEL_xxMARVELL_E1118, MII_STR_xxMARVELL_E1118 },
  { MII_OUI_xxMYSON, MII_MODEL_xxMYSON_MTD972, MII_STR_xxMYSON_MTD972 },
  { MII_OUI_MYSON, MII_MODEL_MYSON_MTD803, MII_STR_MYSON_MTD803 },
  { MII_OUI_xxNATSEMI, MII_MODEL_xxNATSEMI_DP83840, MII_STR_xxNATSEMI_DP83840 },
Index: dev/pci/pcidevs
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs,v
retrieving revision 1.920
diff -u -r1.920 pcidevs
--- dev/pci/pcidevs	26 Nov 2007 09:36:28 -0000	1.920
+++ dev/pci/pcidevs	31 Dec 2007 14:12:39 -0000
@@ -1888,6 +1888,10 @@
 product MARVELL 88SX5041	0x5041	88SX5041 SATA
 product MARVELL 88SX5080	0x5080	88SX5080 SATA
 product MARVELL 88SX5081	0x5081	88SX5081 SATA
+product MARVELL 88F5082		0x5082	88F5082 SoC
+product MARVELL 88F5181		0x5181	88F5181 SoC
+product MARVELL 88F5182		0x5182	88F5182 SoC
+product MARVELL 88F5281		0x5281	88F5281 SoC
 product MARVELL 88SX6041	0x6041	88SX6041 SATA
 product MARVELL 88SX6081	0x6081	88SX6041 SATA
 product MARVELL 88SE6101	0x6101	88SE6101 single-port PATA133 Controller
@@ -1897,6 +1901,7 @@
 product MARVELL	GT64130		0x6320	GT-64130 System Controller
 product MARVELL	GT64260		0x6430	GT-64260 System Controller
 product MARVELL	GT64360		0x6460	MV6436x System Controller
+product MARVELL 88W8660		0x8660	88W8660 SoC
 
 /* Global Sun Tech products */
 product GLOBALSUN GL24110P	0x1101	GL24110P PCI IEEE 802.11b
Index: dev/pci/pcidevs.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs.h,v
retrieving revision 1.921
diff -u -r1.921 pcidevs.h
--- dev/pci/pcidevs.h	9 Dec 2007 20:28:12 -0000	1.921
+++ dev/pci/pcidevs.h	31 Dec 2007 14:12:42 -0000
@@ -1,10 +1,10 @@
-/*	$NetBSD: pcidevs.h,v 1.921 2007/12/09 20:28:12 jmcneill Exp $	*/
+/*	$NetBSD$	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	NetBSD: pcidevs,v 1.885.6.10 2007/10/31 23:14:07 joerg Exp
+ *	NetBSD: pcidevs,v 1.920 2007/11/26 09:36:28 bjs Exp
  */
 
 /*
@@ -1895,6 +1895,10 @@
 #define	PCI_PRODUCT_MARVELL_88SX5041	0x5041		/* 88SX5041 SATA */
 #define	PCI_PRODUCT_MARVELL_88SX5080	0x5080		/* 88SX5080 SATA */
 #define	PCI_PRODUCT_MARVELL_88SX5081	0x5081		/* 88SX5081 SATA */
+#define	PCI_PRODUCT_MARVELL_88F5082	0x5082		/* 88F5082 SoC */
+#define	PCI_PRODUCT_MARVELL_88F5181	0x5181		/* 88F5181 SoC */
+#define	PCI_PRODUCT_MARVELL_88F5182	0x5182		/* 88F5182 SoC */
+#define	PCI_PRODUCT_MARVELL_88F5281	0x5281		/* 88F5281 SoC */
 #define	PCI_PRODUCT_MARVELL_88SX6041	0x6041		/* 88SX6041 SATA */
 #define	PCI_PRODUCT_MARVELL_88SX6081	0x6081		/* 88SX6041 SATA */
 #define	PCI_PRODUCT_MARVELL_88SE6101	0x6101		/* 88SE6101 single-port PATA133 Controller */
@@ -1904,6 +1908,7 @@
 #define	PCI_PRODUCT_MARVELL_GT64130	0x6320		/* GT-64130 System Controller */
 #define	PCI_PRODUCT_MARVELL_GT64260	0x6430		/* GT-64260 System Controller */
 #define	PCI_PRODUCT_MARVELL_GT64360	0x6460		/* MV6436x System Controller */
+#define	PCI_PRODUCT_MARVELL_88W8660	0x8660		/* 88W8660 SoC */
 
 /* Global Sun Tech products */
 #define	PCI_PRODUCT_GLOBALSUN_GL24110P	0x1101		/* GL24110P PCI IEEE 802.11b */
Index: dev/pci/pcidevs_data.h
===================================================================
RCS file: /cvsroot/src/sys/dev/pci/pcidevs_data.h,v
retrieving revision 1.920
diff -u -r1.920 pcidevs_data.h
--- dev/pci/pcidevs_data.h	9 Dec 2007 20:28:12 -0000	1.920
+++ dev/pci/pcidevs_data.h	31 Dec 2007 14:12:44 -0000
@@ -1,10 +1,10 @@
-/*	$NetBSD: pcidevs_data.h,v 1.920 2007/12/09 20:28:12 jmcneill Exp $	*/
+/*	$NetBSD$	*/
 
 /*
  * THIS FILE AUTOMATICALLY GENERATED.  DO NOT EDIT.
  *
  * generated from:
- *	NetBSD: pcidevs,v 1.885.6.10 2007/10/31 23:14:07 joerg Exp
+ *	NetBSD: pcidevs,v 1.920 2007/11/26 09:36:28 bjs Exp
  */
 
 /*
@@ -6564,6 +6564,22 @@
 	    "88SX5081 SATA",
 	},
 	{
+	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5082,
+	    "88F5082 SoC",
+	},
+	{
+	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5181,
+	    "88F5181 SoC",
+	},
+	{
+	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5182,
+	    "88F5182 SoC",
+	},
+	{
+	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88F5281,
+	    "88F5281 SoC",
+	},
+	{
 	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88SX6041,
 	    "88SX6041 SATA",
 	},
@@ -6600,6 +6616,10 @@
 	    "MV6436x System Controller",
 	},
 	{
+	    PCI_VENDOR_MARVELL, PCI_PRODUCT_MARVELL_88W8660,
+	    "88W8660 SoC",
+	},
+	{
 	    PCI_VENDOR_GLOBALSUN, PCI_PRODUCT_GLOBALSUN_GL24110P,
 	    "GL24110P PCI IEEE 802.11b",
 	},
@@ -13960,4 +13980,4 @@
 	    "Video Controller",
 	},
 };
-const int pci_nproducts = 2891;
+const int pci_nproducts = 2896;
